1. Field of the Invention
The present invention relates to generally semiconductor memory devices and a method of operating thereof, more particularly, to a semiconductor memory device in which a physical arrangement of data stored in memory cells in a chip can be adjusted and to a method of adjusting physical arrangements of stored data.
2. Description of the Background Art
FIG. 16 is a diagram showing a conventional semiconductor memory device having a folded bit line structure. In FIG. 16, a plurality of word lines WL1 and WL2 are disposed so as to intersect with a plurality of bit line pairs BL and BL. Memory cells MC are provided at intersections of bit lines BL and word lines WL1, and at intersections of bit lines BL and word lines WL2. A plurality of word lines WL1 and WL2 are connected to a row decoder 3. A sense amplifier 40 is connected between each bit line pair BL and BL. Each bit line pair BL and BL is connected to an input/output line pair I/O and I/ through transistors 5a and 5b. The transistors 5a and 5b are controlled by outputs of a column decoder 6.
Operation of the semiconductor memory device in FIG. 16 will be described. In reading operation, the row decoder 3 selects one of a plurality of word lines WL1 and WL2 to raise its potential. As a result, charge stored in memory cells MC connected to the selected word line is read out onto a corresponding bit line BL or BL. Subsequently, the sense amplifiers 40 are activated so that small potential differences between lines BL and BL are sensed and amplified. Then, the column decoder 6 selects one of transistor pairs 5a and 5b to render conductive, so that the corresponding bit line pair BL and BL is connected to an input/output line pair I/ . In reading operation, the input/output line pair I/O and I/ is connected to a read data line pair 9a and 9b through a switch S. As a result, complementary data RD and RD read out onto the input/output line pair I/O and I/ from the bit line pair BL and BL and is outputted to the external through the read data line pair 9a and 9b and an output buffer (not shown).
In writing operation, at an input buffer (not shown), complementary data WD and WD is generated from data inputted from the external. In writing, a write data line pair 10a and 10b is connected to the input/output line pair I/O and I/ through the switch S, so that the complementary data WD and WD is applied to the input/output line pair I/O and I/ through the write data line pair 10a and 10b. Data on the input/output line pair I/O and I/ is written in a memory cell MC selected in the same manner as that in reading operation.
If data applied from the external is at the logical high level "H", the data WD attains "H" level, and the data WD attains "L" level, so that the data of "H" level is transmitted to the bit line BL, and the data of "L" level to the bit line BL, through the input/output lines I/O and I/ , respectively. Accordingly, when a memory cell MC connected to the bit line BL is selected, data of "H" level is written into the selected memory cell MC. When a memory cell MC connected to the bit line BL is selected, data of "L" level is written into the selected memory cell MC even if the data applied from the external is of "H" level.
Since the semiconductor memory device is constructed as the above, even if data all of which is of "H" level is written from the external, in practice, data of "H" level and "L" level are written into a plurality of memory cells MC as shown in FIG. 17. In FIG. 17, data of "L" level is written into memory cells MC shown with hatching lines and data of 637 H" level is written into the rest of the memory cells MC.
On the other hand, in "ISSCC Digest Technical Papers", pp. 238-239, a twisted bit line is proposed as a bit line structure whereby a dynamic RAM having less noise caused by capacitance between bit lines and enough margin can be implemented. FIG. 18 shows a schematic diagram of a semiconductor memory device having the twisted bit line structure. FIG. 18 corresponds to FIG. 16, and the portions given the same reference characters as those of FIG. 16 denote the corresponding portions in FIG. 16. In FIG. 18, word lines, memory cells and the like are not illustrated so that FIG. 18 can be seen clearly. FIG. 18 is different from FIG. 16 in that bit line pairs BL and BL intersecting each other at points CP1 and CP3, and bit line pairs BL and BL intersecting each other at the points CP2 and CP4 are arranged alternately. Usually, respective blocks a, b, c and d divided respectively at points CP1, CP2, and CP3 have the same length.
FIG. 19 shows a state wherein data all of which is of "H" level is written from the external into an array of a twisted bit line structure. In FIG. 19, data of "L" level is written into memory cells MC shown with hatching lines, and data of "H" level is written into the rest of the memory cells MC. Thus, physical arrangement of data practically stored in a plurality of memory cells MC in a chip is referred to as 637 data scramble".
The possibility of the occurrence of an error depends on physical patterns of data stored in a plurality of memory cells. Therefore, in testing, it is necessary to arrange data in the pattern in which an error tends to occur. However, as is apparent from FIG. 19, in respective blocks a, b, c, and d, arrangements of "H" level data in practice stored in the memory cells MC are different. Therefore, it is difficult to arrange data in a desired pattern. As a result, analysis of defects in testing a semiconductor memory device becomes complicated. More specifically, in a memory tester, data to be written in the memory cell should be changed corresponding to addresses such that data patterns stored in respective blocks a, b, c and d are all the same. Accordingly, a memory tester has a great disadvantage in both hardware and software. Some memory testers do not have such a complicated function, wherein the above analysis of defects of a semiconductor memory device can not be made.
Disclosed in the official gazette of Japanese Patent Laying Open No. 61-160900 is a write/read circuit in which polarity of data written and read to and from RAM in test can be converted. This write/read circuit enables adjustment of arrangements of data stored in memory cells in RAM. However, when a test is performed with this write/read circuit, the circuit needs to be that corresponding to the arrangement of the RAM to be tested. More specifically, when a RAM having an other arrangement is tested, it is necessary to modify the logic of the write/read circuit or the circuit needs to be that corresponding to the arrangement of the RAM. Therefore, handling in test is not simple.